Cadence debuts Maestro chip AI built with Nvidia technology

Cadence Design Systems (CDNS) has introduced Cadence Maestro, a new portfolio of AI models tailored to help design computer chips. The models are built in part on Nvidia (NVDA)’s open-weight Nemotron family and are secured with Nvidia (NVDA)’s OpenShell safety technology. Cadence positions Maestro as a way to automate and enhance electronic design automation workflows by working closely with its existing tools.

The first Maestro models are scheduled to reach select early-access customers in the fourth quarter of 2026. Cadence presents Maestro as part of a broader strategy to embed AI more deeply into chip and system design processes.

Maestro’s models have been fine-tuned on Nvidia’s Nemotron family to interpret and work with the outputs of Cadence’s design, test, and verification tools. Cadence reports that early testing showed up to 30% higher quality of results compared with general-purpose foundation models. The company also cites up to five times better cost-efficiency or token efficiency versus such general-purpose models.

These performance gains are attributed to specialization on chip-design data and tight integration with Cadence’s environment. The Maestro platform also supports customization based on customer data, with Cadence indicating that such tailoring will be offered as a managed service rather than leaving customers to configure it entirely on their own.

Cadence states that Maestro can run on its own cloud infrastructure, on any public cloud, or entirely within a customer’s data centers behind their firewalls. Customers can fine-tune the models on their own proprietary chip designs while keeping those designs on infrastructure they control. Maestro models and agents can be accessed via API, deployed in a secure virtual private cloud, or run on-premises when the necessary hardware is available.

This deployment flexibility is presented as a way to align AI adoption with existing enterprise rules for handling sensitive design data. By enabling both cloud-based and on-premises options, Maestro is intended to accommodate varied security and compliance requirements among chipmakers and system designers.

Cadence’s approach with Maestro contrasts with a Synopsys chip-design AI model, GPT-Synopsys, which is planned to run on infrastructure hosted by OpenAI. Cadence senior vice president Paul Cunningham describes Maestro as model-agnostic, noting that there are more AI model providers than chip design software vendors. He also indicates that both open- and closed-weight approaches are being pursued, and that working with commercial AI labs is "part of the Maestro vision."

Maestro builds on Cadence’s previously introduced AI Super Agents such as AuraStack for advanced packaging and PCB layout, ChipStack for system-on-chip design and verification, InnoStack for PHY routing, and ViraStack for analog circuit design. These agents orchestrate Cadence’s EDA, test, and verification tools using large language models, and Maestro provides specialized models to improve their effectiveness in automating design and validation flows.

Cadence characterizes Maestro and its AI agents as examples of how generative AI can work alongside high-performance computing in chip and system design. The models are intended to interpret design intent, decompose tasks, and orchestrate Maestro with other frontier and open-weight models while evaluating trade-offs with domain expertise. This reflects a wider industry effort to use AI agents to manage complex design and compute workflows across specialized hardware and software stacks.