Key Points
- 01Samsung unveils V10 Bonding V-NAND with over 400 layers
- 02New BV-NAND prototype targets higher density and performance
- 03Concept zHBM and zNAND-O introduce 3D-stacked AI memory designs
- 04Wafer-bonding aims for over 10x density versus conventional HBM5
Samsung introduces next-wave AI memory
Samsung Electronics has presented a new generation of memory technologies designed for artificial-intelligence workloads, highlighting advances in 3D stacking and wafer bonding. The company’s roadmap centers on boosting storage density, data throughput and energy efficiency to meet rising requirements from AI accelerators and data-centric systems.
At the core of the announcement is a V10 Bonding V-NAND (BV-NAND) prototype that uses a wafer-bonding architecture and more than 400 layers. This design is intended to pack more bits into a given footprint while enhancing read, write and input/output performance for data-intensive tasks.
V10 BV-NAND and density gains
Samsung reports that the V10 BV-NAND achieves roughly a 58% density gain compared with its previous V9 NAND generation. By combining high layer counts with wafer bonding, the company aims to substantially increase capacity per chip, a key metric for storage devices supporting AI training and inference.
The BV-NAND approach is positioned to support higher performance as well as density. Improvements in I/O operations and internal data paths are described as central to enabling faster access to large data sets, which are typical in modern machine-learning pipelines.
Concept zHBM and zNAND-O architectures
Alongside BV-NAND, Samsung showcased concept models referred to as zHBM and zNAND-O, described as next-generation 3D memory designs. These architectures rely on vertically stacked memory cells, allowing greater capacity in a compact footprint for use alongside advanced processors.
Samsung outlined zHBM as stacking memory above AI accelerators rather than positioning high-bandwidth memory alongside processors. This layout is intended to shorten data travel distances, providing higher bandwidth and improving overall energy efficiency in AI systems.
Wafer bonding and future AI infrastructure
The company stated that its wafer-bonding techniques could enable more than a tenfold increase in memory density compared with conventional HBM5 memory. It also indicated that this approach could roughly triple energy efficiency and cut thermal resistance by more than half.
These projected gains suggest a path for scaling AI infrastructure with denser, faster and cooler memory subsystems. By combining V10 BV-NAND with emerging zHBM and zNAND-O concepts, Samsung is outlining a 3D-memory roadmap that targets the performance and efficiency needs of next-generation AI workloads.
Key Takeaways
- 01Samsung is positioning wafer-bonded, 3D-stacked memory as a key enabler for denser and more efficient AI hardware.
- 02The V10 BV-NAND prototype demonstrates a substantial density increase over Samsung’s prior V9 NAND generation.
- 03zHBM highlights placing memory directly above AI accelerators to reduce data movement and power use, while zNAND-O focuses on vertically stacked cells to increase capacity in a compact footprint.